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author | cvs2svn <> | 2009-09-04 04:29:43 +0000 |
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committer | cvs2svn <> | 2009-09-04 04:29:43 +0000 |
commit | 6144d92bc7dc5b75e7bc5e04227c0ba1581d28cb (patch) | |
tree | c38dcebde7d1c6cb4810ccaa52d4016699da3574 /include/gdb/sim-sh.h | |
parent | 5cbd59b72a754824f6f13459279c0bdf11c686f1 (diff) | |
download | cygnal-cgen-snapshot-20090901.tar.gz cygnal-cgen-snapshot-20090901.tar.bz2 cygnal-cgen-snapshot-20090901.zip |
This commit was manufactured by cvs2svn to create tag 'cgen-cgen-snapshot-20090901
snapshot-20090901'.
Sprout from binutils-2_20-branch 2009-09-04 04:29:41 UTC cvs2svn 'This commit was manufactured by cvs2svn to create branch 'binutils-'
Cherrypick from master 2009-09-01 13:38:26 UTC Tristan Gingold <gingold@adacore.com> '2009-09-01 Tristan Gingold <gingold@adacore.com>':
ChangeLog
Makefile.def
Makefile.in
Makefile.tpl
configure
configure.ac
Delete:
include/COPYING
include/COPYING3
include/ChangeLog
include/ChangeLog-9103
include/MAINTAINERS
include/alloca-conf.h
include/ansidecl.h
include/aout/ChangeLog
include/aout/adobe.h
include/aout/aout64.h
include/aout/ar.h
include/aout/dynix3.h
include/aout/encap.h
include/aout/host.h
include/aout/hp.h
include/aout/hp300hpux.h
include/aout/hppa.h
include/aout/ranlib.h
include/aout/reloc.h
include/aout/stab.def
include/aout/stab_gnu.h
include/aout/sun4.h
include/bfdlink.h
include/binary-io.h
include/bout.h
include/coff/ChangeLog
include/coff/ChangeLog-9103
include/coff/alpha.h
include/coff/apollo.h
include/coff/arm.h
include/coff/aux-coff.h
include/coff/ecoff.h
include/coff/external.h
include/coff/go32exe.h
include/coff/h8300.h
include/coff/h8500.h
include/coff/i386.h
include/coff/i860.h
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include/coff/ia64.h
include/coff/internal.h
include/coff/m68k.h
include/coff/m88k.h
include/coff/maxq.h
include/coff/mcore.h
include/coff/mips.h
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include/coff/or32.h
include/coff/pe.h
include/coff/powerpc.h
include/coff/rs6000.h
include/coff/rs6k64.h
include/coff/sh.h
include/coff/sparc.h
include/coff/sym.h
include/coff/symconst.h
include/coff/ti.h
include/coff/tic30.h
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include/coff/tic80.h
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include/demangle.h
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include/dyn-string.h
include/elf/ChangeLog
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include/elf/alpha.h
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include/elf/avr.h
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include/elf/mt.h
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include/elf/ppc.h
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include/elf/reloc-macros.h
include/elf/s390.h
include/elf/score.h
include/elf/sh.h
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include/elf/x86-64.h
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include/fopen-bin.h
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include/gdb/ChangeLog
include/gdb/callback.h
include/gdb/fileio.h
include/gdb/remote-sim.h
include/gdb/signals.h
include/gdb/sim-arm.h
include/gdb/sim-cr16.h
include/gdb/sim-d10v.h
include/gdb/sim-frv.h
include/gdb/sim-h8300.h
include/gdb/sim-lm32.h
include/gdb/sim-m32c.h
include/gdb/sim-ppc.h
include/gdb/sim-sh.h
include/gdbm.h
include/getopt.h
include/hashtab.h
include/hp-symtab.h
include/ieee.h
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include/md5.h
include/nlm/ChangeLog
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include/nlm/external.h
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include/oasys.h
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include/opcode/ChangeLog
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include/opcode/alpha.h
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include/opcode/avr.h
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include/opcode/cgen-bitset.h
include/opcode/cgen.h
include/opcode/convex.h
include/opcode/cr16.h
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include/opcode/ia64.h
include/opcode/m68hc11.h
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include/opcode/maxq.h
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include/opcode/mn10200.h
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include/opcode/moxie.h
include/opcode/msp430.h
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include/opcode/pn.h
include/opcode/ppc.h
include/opcode/pyr.h
include/opcode/s390.h
include/opcode/score-datadep.h
include/opcode/score-inst.h
include/opcode/sparc.h
include/opcode/spu-insns.h
include/opcode/spu.h
include/opcode/tahoe.h
include/opcode/tic30.h
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include/opcode/tic80.h
include/opcode/v850.h
include/opcode/vax.h
include/os9k.h
include/partition.h
include/plugin-api.h
include/progress.h
include/safe-ctype.h
include/sha1.h
include/sort.h
include/splay-tree.h
include/symcat.h
include/xregex.h
include/xregex2.h
include/xtensa-config.h
include/xtensa-isa-internal.h
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texinfo/texinfo.tex
Diffstat (limited to 'include/gdb/sim-sh.h')
-rw-r--r-- | include/gdb/sim-sh.h | 170 |
1 files changed, 0 insertions, 170 deletions
diff --git a/include/gdb/sim-sh.h b/include/gdb/sim-sh.h deleted file mode 100644 index 3c611769e..000000000 --- a/include/gdb/sim-sh.h +++ /dev/null @@ -1,170 +0,0 @@ -/* This file defines the interface between the sh simulator and gdb. - Copyright (C) 2000, 2002, 2004, 2007, 2008, 2009 - Free Software Foundation, Inc. - - This file is part of GDB. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see <http://www.gnu.org/licenses/>. */ - -#if !defined (SIM_SH_H) -#define SIM_SH_H - -#ifdef __cplusplus -extern "C" { // } -#endif - -/* The simulator makes use of the following register information. */ - -enum -{ - SIM_SH_R0_REGNUM = 0, - SIM_SH_R1_REGNUM, - SIM_SH_R2_REGNUM, - SIM_SH_R3_REGNUM, - SIM_SH_R4_REGNUM, - SIM_SH_R5_REGNUM, - SIM_SH_R6_REGNUM, - SIM_SH_R7_REGNUM, - SIM_SH_R8_REGNUM, - SIM_SH_R9_REGNUM, - SIM_SH_R10_REGNUM, - SIM_SH_R11_REGNUM, - SIM_SH_R12_REGNUM, - SIM_SH_R13_REGNUM, - SIM_SH_R14_REGNUM, - SIM_SH_R15_REGNUM, - SIM_SH_PC_REGNUM, - SIM_SH_PR_REGNUM, - SIM_SH_GBR_REGNUM, - SIM_SH_VBR_REGNUM, - SIM_SH_MACH_REGNUM, - SIM_SH_MACL_REGNUM, - SIM_SH_SR_REGNUM, - SIM_SH_FPUL_REGNUM, - SIM_SH_FPSCR_REGNUM, - SIM_SH_FR0_REGNUM, /* FRn registers: sh3e / sh4 */ - SIM_SH_FR1_REGNUM, - SIM_SH_FR2_REGNUM, - SIM_SH_FR3_REGNUM, - SIM_SH_FR4_REGNUM, - SIM_SH_FR5_REGNUM, - SIM_SH_FR6_REGNUM, - SIM_SH_FR7_REGNUM, - SIM_SH_FR8_REGNUM, - SIM_SH_FR9_REGNUM, - SIM_SH_FR10_REGNUM, - SIM_SH_FR11_REGNUM, - SIM_SH_FR12_REGNUM, - SIM_SH_FR13_REGNUM, - SIM_SH_FR14_REGNUM, - SIM_SH_FR15_REGNUM, - SIM_SH_SSR_REGNUM, /* sh3{,e,-dsp}, sh4 */ - SIM_SH_SPC_REGNUM, /* sh3{,e,-dsp}, sh4 */ - SIM_SH_R0_BANK0_REGNUM, /* SIM_SH_Rn_BANKm_REGNUM: sh3[e] / sh4 */ - SIM_SH_R1_BANK0_REGNUM, - SIM_SH_R2_BANK0_REGNUM, - SIM_SH_R3_BANK0_REGNUM, - SIM_SH_R4_BANK0_REGNUM, - SIM_SH_R5_BANK0_REGNUM, - SIM_SH_R6_BANK0_REGNUM, - SIM_SH_R7_BANK0_REGNUM, - SIM_SH_R0_BANK1_REGNUM, - SIM_SH_R1_BANK1_REGNUM, - SIM_SH_R2_BANK1_REGNUM, - SIM_SH_R3_BANK1_REGNUM, - SIM_SH_R4_BANK1_REGNUM, - SIM_SH_R5_BANK1_REGNUM, - SIM_SH_R6_BANK1_REGNUM, - SIM_SH_R7_BANK1_REGNUM, - SIM_SH_XF0_REGNUM, - SIM_SH_XF1_REGNUM, - SIM_SH_XF2_REGNUM, - SIM_SH_XF3_REGNUM, - SIM_SH_XF4_REGNUM, - SIM_SH_XF5_REGNUM, - SIM_SH_XF6_REGNUM, - SIM_SH_XF7_REGNUM, - SIM_SH_XF8_REGNUM, - SIM_SH_XF9_REGNUM, - SIM_SH_XF10_REGNUM, - SIM_SH_XF11_REGNUM, - SIM_SH_XF12_REGNUM, - SIM_SH_XF13_REGNUM, - SIM_SH_XF14_REGNUM, - SIM_SH_XF15_REGNUM, - SIM_SH_SGR_REGNUM, - SIM_SH_DBR_REGNUM, - SIM_SH4_NUM_REGS, /* 77 */ - - /* sh[3]-dsp */ - SIM_SH_DSR_REGNUM, - SIM_SH_A0G_REGNUM, - SIM_SH_A0_REGNUM, - SIM_SH_A1G_REGNUM, - SIM_SH_A1_REGNUM, - SIM_SH_M0_REGNUM, - SIM_SH_M1_REGNUM, - SIM_SH_X0_REGNUM, - SIM_SH_X1_REGNUM, - SIM_SH_Y0_REGNUM, - SIM_SH_Y1_REGNUM, - SIM_SH_MOD_REGNUM, - SIM_SH_RS_REGNUM, - SIM_SH_RE_REGNUM, - SIM_SH_R0_BANK_REGNUM, - SIM_SH_R1_BANK_REGNUM, - SIM_SH_R2_BANK_REGNUM, - SIM_SH_R3_BANK_REGNUM, - SIM_SH_R4_BANK_REGNUM, - SIM_SH_R5_BANK_REGNUM, - SIM_SH_R6_BANK_REGNUM, - SIM_SH_R7_BANK_REGNUM, - /* 109..127: room for expansion. */ - SIM_SH_TBR_REGNUM, - SIM_SH_IBNR_REGNUM, - SIM_SH_IBCR_REGNUM, - SIM_SH_BANK_REGNUM, - SIM_SH_BANK_MACL_REGNUM, - SIM_SH_BANK_GBR_REGNUM, - SIM_SH_BANK_PR_REGNUM, - SIM_SH_BANK_IVN_REGNUM, - SIM_SH_BANK_MACH_REGNUM -}; - -enum -{ - SIM_SH64_R0_REGNUM = 0, - SIM_SH64_SP_REGNUM = 15, - SIM_SH64_PC_REGNUM = 64, - SIM_SH64_SR_REGNUM = 65, - SIM_SH64_SSR_REGNUM = 66, - SIM_SH64_SPC_REGNUM = 67, - SIM_SH64_TR0_REGNUM = 68, - SIM_SH64_FPCSR_REGNUM = 76, - SIM_SH64_FR0_REGNUM = 77 -}; - -enum -{ - SIM_SH64_NR_REGS = 141, /* total number of architectural registers */ - SIM_SH64_NR_R_REGS = 64, /* number of general registers */ - SIM_SH64_NR_TR_REGS = 8, /* number of target registers */ - SIM_SH64_NR_FP_REGS = 64 /* number of floating point registers */ -}; - -#ifdef __cplusplus -} -#endif - -#endif |