From d52dd126b35bfa0f6139a2dd4fb547493ed447bd Mon Sep 17 00:00:00 2001 From: Kaz Kylheku Date: Wed, 18 Apr 2018 20:25:22 -0700 Subject: asm: disassembler v-reg regression. * share/txr/stdlib/asm.tl (operand-to-sym): To form v registers, we must subtract 2 from the level, not add. (operand-to-exp): Bug was propagated to this new function, too. --- share/txr/stdlib/asm.tl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'share') diff --git a/share/txr/stdlib/asm.tl b/share/txr/stdlib/asm.tl index ed7ae1a0..edf0b67a 100644 --- a/share/txr/stdlib/asm.tl +++ b/share/txr/stdlib/asm.tl @@ -283,7 +283,7 @@ nil (intern (fmt "t~,02X" ix)))) (1 (intern (fmt "d~,02X" ix))) - (t (intern (fmt "v~,02X~,03X" (ssucc lv) ix)))))) + (t (intern (fmt "v~,02X~,03X" (ppred lv) ix)))))) (defun operand-to-exp (val) (with-lev-idx (lv ix) val @@ -292,7 +292,7 @@ nil ^(t ,ix))) (1 ^(d ,ix)) - (t ^(v ,lv ,ix))))) + (t ^(v ,(ppred lv) ,ix))))) (defun bits-to-obj (bits width) (let ((tag (logtrunc bits 2)) -- cgit v1.2.3