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| author | Kaz Kylheku <kaz@kylheku.com> | 2019-11-29 22:29:22 -0800 |
|---|---|---|
| committer | Kaz Kylheku <kaz@kylheku.com> | 2019-11-29 22:29:22 -0800 |
| commit | eec7b1fdc2fa0d53bef990d6cc2339354d57067a (patch) | |
| tree | 36d064a9be40306fded9070f8781d8b0a00a4d51 | |
| parent | 91d2751f4fddaf80bd75d54f1bb62c5960ebdb7d (diff) | |
| download | txr-eec7b1fdc2fa0d53bef990d6cc2339354d57067a.tar.gz txr-eec7b1fdc2fa0d53bef990d6cc2339354d57067a.tar.bz2 txr-eec7b1fdc2fa0d53bef990d6cc2339354d57067a.zip | |
disassemble: d and t regs in decimal.
* share/txr/stdlib/asm.tl (operand-to-sym): Use decimal
with no leading zeros for t and d registers. Only the v
registers use hex, because that helps unravel their level
structure. The data table is dumped with decimal numbering, so
the d registers being decimal makes it easier to cross-ref.
| -rw-r--r-- | share/txr/stdlib/asm.tl | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/share/txr/stdlib/asm.tl b/share/txr/stdlib/asm.tl index 06a6b258..ffef617c 100644 --- a/share/txr/stdlib/asm.tl +++ b/share/txr/stdlib/asm.tl @@ -278,8 +278,8 @@ (caseql lv (0 (if (zerop ix) nil - (intern (fmt "t~,03X" ix)))) - (1 (intern (fmt "d~,03X" ix))) + (intern (fmt "t~s" ix)))) + (1 (intern (fmt "d~s" ix))) (t (intern (fmt "v~,02X~,03X" (ppred lv) ix)))))) (defun operand-to-exp (val) |