From 7040b2de0883e8346af9c976cd711cf75307e854 Mon Sep 17 00:00:00 2001 From: Kito Cheng Date: Thu, 27 Jul 2017 16:45:12 +0800 Subject: Add RISC-V port for libm Contributor list: - Michael Neilly - Kito Cheng --- newlib/libm/machine/riscv/fetestexcept.c | 77 ++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 newlib/libm/machine/riscv/fetestexcept.c (limited to 'newlib/libm/machine/riscv/fetestexcept.c') diff --git a/newlib/libm/machine/riscv/fetestexcept.c b/newlib/libm/machine/riscv/fetestexcept.c new file mode 100644 index 000000000..55d880c99 --- /dev/null +++ b/newlib/libm/machine/riscv/fetestexcept.c @@ -0,0 +1,77 @@ +/* + (c) Copyright 2017 Michael R. Neilly + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the names of the copyright holders nor the names of their + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + +#include + +/* This implementation is intended to comply with the following + * specification: + * + * http://pubs.opengroup.org/onlinepubs/9699919799/functions/fetestexcept.html + * + * "The fetestexcept() function shall determine which of a specified + * subset of the floating-point exception flags are currently set. The + * excepts argument specifies the floating-point status flags to be + * queried." + */ + +int fetestexcept(int excepts) +{ + +#if __riscv_flen + + /* Mask excepts to be sure only supported flag bits are set */ + + excepts &= FE_ALL_EXCEPT; + + /* Read the current flags */ + + fexcept_t flags; + asm volatile("frflags %0" : "=r"(flags)); + + /* "The fetestexcept() function shall return the value of the + * bitwise-inclusive OR of the floating-point exception macros + * corresponding to the currently set floating-point exceptions + * included in excepts." + */ + + return (flags & excepts); + +#else + + /* For soft float */ + + return 0; + +#endif + +} -- cgit v1.2.3