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* Add RISC-V port for libglossnewlib-snapshot-20170818Kito Cheng2017-08-179-0/+4340
| | | | | | | | Contributor list: - Andrew Waterman <andrew@sifive.com> - Palmer Dabbelt <palmer@dabbelt.com> - Kito Cheng <kito.cheng@gmail.com> - Alex Suykov <alex.suykov@gmail.com>
* Fix crt0 init fini codeSzabolcs Nagy2017-08-171-4/+0
| | | | | __USES_INITFINI__ ifdef was incorrectly copied from arm (it's an arm backend thing in gcc, not meaningful on aarch64)
* fix typo in AArch64 crt0Alexander Fedotov-B556132017-08-151-1/+1
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* use stack from linker script when nosysAlexander Fedotov-B556132017-08-141-1/+18
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* Don't fetch command line options without semi-hostingYao Qi2017-08-091-0/+6
| | | | | | | | | | | | | | | | | Nowadays, the code fetching command line options via semi-hosting are unconditionally pulled in, so that the semi-hosting code is still there even I compile with option --specs=nosys.specs. gdb ./aarch64-none-elf/libgloss/aarch64/crt0.o (gdb) disassemble _start 0x0000000000000050 <+80>: ldr x1, 0x128 <_cpu_init_hook+48> 0x0000000000000054 <+84>: mov w0, #0x15 0x0000000000000058 <+88>: hlt #0xf000 This patch fixes this problem by wrapping the code by ARM_RDI_MONITOR. When semi-hosting is not used, set command line options to NULL.
* Fix crt0 overwriting.Tamar Christina2017-08-094-1/+10
| | | | | | | | | | | On AArch64 we currently always link in crt0 regardless of if another one is being provided by something else, like rdimon.a. This was never an issue before as nosys was not supported on AArch64. This updates the specs to supply a different crt0 when a semihosting call is required. Signed-off-by: Tamar Christina <tamar.christina@arm.com>
* Previous patch to support nosys.specs accidentally broke validation specs ↵Tamar Christina2017-07-211-1/+1
| | | | | | | | | | | | because ARM_RDI_MONITOR was never passed to the build rule for crt0. This fixed the compile for nosys and validation specs but nosys won't run because of existing limitations to aarch64's syscalls.c, it requires semihosting to get commandline arguments and heap info without having a fallback method as ARM does. Signed-off-by: Tamar Christina <tamar.christina@arm.com>
* Support building in a different directory than the default output directory ↵Tamar Christina2017-07-171-1/+1
| | | | | | by preserving DESTDIR value in recursive calls. Signed-off-by: Tamar Christina <tamar.christina@arm.com>
* Fix link when nosys.specs is used to linkTamar Christina2017-07-141-0/+2
| | | | | | | | This patch fixes the issue where nosys.specs is used to link. e.g. The use of crt0 without any support for semihosting requested. The AArch64 crt0 was missing an #ifdef for the initialise_monitor_handles which was causing the link to fail. Sorry for missing this before.
* Replace the perl character classes with POSIX ones to fix the build when sed ↵Tamar Christina2017-07-061-4/+4
| | | | | | is a BSD sed instead of GNU. Signed-off-by: Tamar Christina <tamar.christina@arm.com>
* Add support for Semihosting v2 support for AArch64 in libgloss.Tamar Christina2017-07-054-47/+186
| | | | | | | | | | Semihosting v2 changes are documented here: https://developer.arm.com/docs/100863/latest/ The biggest change is the addition of an extensions mechanism to add more extensions in the future. Signed-off-by: Tamar Christina <tamar.christina@arm.com>
* Add support for Semihosting v2 support for ARM in libgloss.Tamar Christina2017-07-053-65/+231
| | | | | | | | | | Semihosting v2 changes are documented here: https://developer.arm.com/docs/100863/latest/ The biggest change is the addition of an extensions mechanism to add more extensions in the future. Signed-off-by: Tamar Christina <tamar.christina@arm.com>
* Add the needed build system changes in order to compile and create the new ↵Tamar Christina2017-07-059-17/+147
| | | | | | | | | | | | | | | | | | libraries for Semihosting v2 for ARM. This uses the new recursive build target in multi-build.in The new spec files are: For AArch32/ARM (m for mixed mode): - rdimon-v2m.specs - aprofile-validation-v2m.specs - aprofile-ve-v2m.specs These spec files will be using the new libraries generated by multi-build.in. Signed-off-by: Tamar Christina <tamar.christina@arm.com>
* Adds the needed build system changes in order to compile and create the new ↵Tamar Christina2017-07-054-16/+49
| | | | | | | | | | | libraries for Semihosting v2. This uses the new recursive build target in multi-build.in For AArch64 no new spec files are needed but the makefiles are modified to keep them in sync with the ARM ones. Signed-off-by: Tamar Christina <tamar.christina@arm.com>
* Create a recursive make target that is modeled after the existing multilib ↵Tamar Christina2017-07-051-0/+61
| | | | | | | | | makefile config-ml.in which can be used to build the same files within a target multiple ways. e.g. from the same source file produce multiple libs by varying the options passed to the compiler. Signed-off-by: Tamar Christina <tamar.christina@arm.com>
* Add JLI support.Claudiu Zissulescu2017-06-141-1/+6
| | | | | | | | | Initialize the jli_base registers for ARCv2 cpus. libgloss/ 2017-05-23 Claudiu Zissulescu <claziss@synopsys.com> * arc/crt0.S: Initialize the jli_base registers for ARCv2 cpus.
* Add profile support.Claudiu Zissulescu2017-06-144-8/+527
| | | | | | | | | | | | | | Add profile support for ARC processors. libgloss/ 2016-07-28 Claudiu Zissulescu <claziss@synopsys.com> * arc/crt0.S: Add calls to profiler support routines. * Makefile.in (CRT0): Add gcrt0. (NSIM_OBJS): Add mcount. (CRT0_INSTALL): Install gcrt0, and crt0. * arc/gcrt0.S: New file. * arc/mcount.c: Likewise.
* Fix thinko in MSP430 libgloss implementation of write() system call.Martin Young2017-05-261-1/+1
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* ARM/AArch64: Fix GetCmdLine semihosting directivesnewlib-snapshot-20170519Laurent ALFONSI2017-05-192-7/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When simulating arm code, the target program startup code (crt0) uses semihosting invocations to get the command line from the simulator. The simulator returns the command line and its size into the area passed in parameter. (ARM 32-bit specifications : http://infocenter.arm.com/help/topic/com.arm.doc.dui0058d/DUI0058.pdf chapter "5.4.19 SYS_GET_CMDLINE"). The memory area pointed by the semihosting register argument is located in .text section (usually not writtable (RX)). If we run this code on a simulator that respects this rights properties (qemu user-mode for instance), the command line will not be written to the .text program memory, in particular the length of the string. The program runs with an empty command line. This problem hasn't been seen earlier probably because qemu user-mode is not so much used, but this can happen with another simulator that refuse to write in a read-only segment. With this modification, the command line can be correctly passed to the target program. Changes: - libgloss/arm/crt0.S : Arguments passed to the AngelSWI_Reason_GetCmdLine semihosting invocation are placed into .data section instead of .text - libgloss/aarch64/crt0.S : Idem for aarch64 AngelSVC_Reason_GetCmdLine semihosting.
* Fix relocation type for _bsssize being R_MSP430X_ABS16 when large memory ↵Jozef Lawrynowicz2017-04-191-2/+2
| | | | model is used
* libgloss/arm: fix discovery of "eabihf" toolchainsCarlos Santos2017-04-182-2/+2
| | | | | | | | | | | | | ARM EABI toolchains can optionally use the "hf" suffix to identify hardware floating point support. Use the "*-*-eabi*" pattern to match these toolchains. Original patch by Bryan Hundven for the Crosstool-NG project. Improved by Alexey Neyman. Signed-off-by: Carlos Santos <casantos@datacom.ind.br> CC: Bryan Hundven <bryanhundven@gmail.com CC: Alexey Neyman <stilor@att.net>
* Fix elf-nano.specs to work without -save-tempsThomas Preud'homme2017-02-151-3/+3
| | | | | | | | | | | | The changes in af272aca591fe1dc0f1be64ae5bda147ea98a047 only works when using gcc/g++ with -E or -save-temps, otherwise newlib's newlib.h gets used even if -specs=nano.specs is specified. This is because the driver only use cpp_options spec for the external cpp tool, not for the integrated one. This patch uses instead cpp_unique_options which is used in all cases: it is used directly when the integrated preprocessor is used, and indirectly by expansion of cpp_options otherwise.
* Fix cpp invocation for C++ in nano specThomas Preudhomme2017-02-131-3/+3
| | | | | | | | | | | Hi, The changes in c028685518a261f6d0dab0d7ed15f9570ab9b3d0 to use newlib-nano's include directory work for cc1 but not cc1plus. cc1plus comes with its own cpp spec which does not have a name attached to it. This patch uses the renaming trick on cpp_options instead of cpp, as cpp_options is used both by cc1 and cc1plus.
* libgloss: Remove duplicate definition of environStafford Horne2017-02-131-3/+0
| | | | | | | | | | | | | | | | Environ is defined in libgloss and libc: - libgloss/or1k/syscalls.c - libc/stdlib/environ.c When linking we sometimes get errors: or1k-elf-g++ test.o -mnewlib -mboard=or1ksim -lm -o test /opt/shorne/software/or1k/lib/gcc/or1k-elf/5.3.0/../../../../or1k-elf/lib/libor1k.a(syscalls.o):(.data+0x0): multiple definition of `environ' /opt/shorne/software/or1k/lib/gcc/or1k-elf/5.3.0/../../../../or1k-elf/lib/libc.a(lib_a-environ.o):(.data+0x0): first defined here collect2: error: ld returned 1 exit status This doesnt happen after the fix. Basic things build fine too.
* libgloss: or1k: If available call the init for init_arrayStafford Horne2017-02-131-0/+6
| | | | | | | | | There was an issue revealed in gdb testing where C++ virtual tables were not getting properly initialized. This seems to be due to the c++ global constructors moving from ctors to init_array. This fix makes sure we call the proper method for initializing the constructors in all places.
* or1k: Make open reentrantOlof Kindgren2017-02-131-1/+1
| | | | | | | | | | | or1k uses reentrant calls by default, but there was no open_r defined which caused failure in C++/C code such as: int main() { std::cout << "test\n"; return 0; } or int main() {open(".", 0);}
* Committed, libgloss: hook up cris-elf to the initfini-array support.Hans-Peter Nilsson2017-01-292-2/+15
| | | | | | | | | | | | | | | | | | After a binutils change "a while ago" (2015-12) to default to --enable-initfini-array, i.e. to merge .ctors and .dtors into .init_array and .fini_array, this is needed for cdtors to run at all. Based on what goes on in arm/ and aarch64/. Tested for cris-elf by running the gcc testsuite. By the way, the configure test doesn't detect this change, so the HAVE_INITFINI_ARRAY ifdeffery is somewhat redundant. Still, the change is tested to be safe with older binutils too. libgloss/ * cris/crt0.S, cris/lcrt0.c: Include newlib.h. [HAVE_INITFINI_ARRAY] (_init): Define to __libc_init_array. [HAVE_INITFINI_ARRAY] (_fini): Ditto __libc_fini_array.
* Fix html build with makeinfo 5.2Thomas Preudhomme2016-08-191-2/+2
| | | | | | | | | | | HTML build fails with makeinfo 5.2 with the following error: libgloss/doc/porting.texi:73: @menu seen before first @node libgloss/doc/porting.texi:73: perhaps your @top node should be wrapped in @ifnottex rather than @ifinfo? Following the advice indeed solve the issue while still allowing pdf, dvi and info builds to work.
* arc: Add align keyword.Claudiu Zissulescu2016-08-111-2/+2
| | | | | | | libgloss/ 2016-06-28 Claudiu Zissulescu <claziss@synopsys.com> * arc/crt0.S: Add align keyword.
* Add comment in the v850's crt0.S file noting that separate LMA and VMA ↵newlib-snapshot-20160527Nick Clifton2016-05-261-0/+9
| | | | addresses for data sections are not currently supported.
* arc: Have nops in _exit_halt only for ARCompactAnton Kolesov2016-05-251-6/+9
| | | | | | | | | | | ARCompact processors (ARC 600 and ARC 700) require three "nop"s after the "flag 1" instruction. Later ARC processors do not have this requirement, so it is possible to reduce size of "_exit_halt" for them. libgloss/ 2016-05-24 Anton Kolesov <Anton.Kolesov@synopsys.com> * arc/crt0.S (_exit_halt): Insert nops only for ARCompact.
* arc: Rework default exception handlers for ARC EM and HSAnton Kolesov2016-05-251-73/+34
| | | | | | | | | | | | | | | | | | | | | | Initially crt0.S used a special function, declared as weak as a default exception handler in interrupt vector table. To let user override individual handlers, this function had multiple names - one for each IVT entry, which, however, was terribly confusing for the debugger and user - because it wasn't clear which symbol will be used as a function name in debugger. Defining multiple separate functions - one for each handler, would resolve the mess, but would increase code size of crt0.o. To clean this up, this patch defines exception handlers as weak symbols as well, but those are defined as just symbols, not functions, hence there would be less confusion over what is what. At the same time, users still can redefine exception handlers symbol by creating functions with respective names. libgloss/ 2016-05-24 Anton Kolesov <Anton.Kolesov@synopsys.com> * arc/crt0.S: Convert memory_error and friends to non-function symbols.
* libgloss/ft32: fix whitespace in MakefileYaakov Selkowitz2016-05-201-29/+29
| | | | Signed-off-by: Yaakov Selkowitz <yselkowi@redhat.com>
* Fix libgloss arc nsim specs file.Jeff Johnston2016-05-111-1/+1
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* Fix libgloss/arc/nano.specs file.Jeff Johnston2016-05-061-2/+2
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* Fix white-space in libgloss/arc/Makefile.in.Jeff Johnston2016-05-051-3/+3
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* Fix support ARC processors without barrel-shifterJeff Johnston2016-05-021-1/+6
| | | | | | | | | | | | | | | | | crt0.S for ARC used to use instruction "asr.f lp_count, r3, 2" for all cores except ARC601. However instructions which shift more than 1 bit are optional, so this crt0.S didn't worked for all ARC cores. Luckily this is a shift just by 2 bits on all occassions, so fix is trivial - use two single-bit shifts. libgloss/ChangeLog 2016-04-29 Anton Kolesov <anton.kolesov@synopsys.com> * arc/crt0.S: Fix support for processors without barrel-shifter. Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>
* Update crt0.S for ARC.Jeff Johnston2016-05-021-9/+23
| | | | | | | | | | | | | | | | | | | | | | | | | This is similar to commit 06537f05d4b6a0d2db01c6afda1d2a0ea2588126 to the newlib for ARC. GCC for ARC has been updated to provide consistent naming of preprocessor definitions for different optional architecture features: * __ARC_BARREL_SHIFTER__ instead of __Xbarrel_shifter for -mbarrel-shifter * __ARCEM__ instead of __EM__ for ARC EM cores * __ARCHS__ instead of __HS__ for ARC HS cores * etc (not used in libgloss) This patch updates crt0.S for ARC to use new definitions instead of a deprecated ones. To ensure compatibility with older compiler new definitions are also defined in crt0.S if needed, based on presence of deprecated preprocessor definitions. libgloss/ChangeLog 2016-04-29 Anton Kolesov <Anton.Kolesov@synopsys.com> * arc/crt0.S: Use new GCC defines to detect processor features.
* Add necessary infrastructure to support "nano" build of newlib.Jeff Johnston2016-04-293-3/+35
| | | | | | | | | | ARC aproach to this feature is similiar to ARM's one here. 2016-04-29 Anton Kolesov <anton.kolesov@synopsys.com> * arc/nano.specs: New file. * arc/Makefile.in: Support nano.specs. * arc/nsim.specs: Likewise.
* Fixed semihosting for ARM when heapinfo not provided by debugger.David Hoover2016-04-211-1/+3
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* Fix typo in the name of the MSP430 attribute section of example MSP430 ↵Nick Clifton2016-04-072-2/+2
| | | | linker scripts.
* Initializing TTBR0 to inner/outer WBJiong Wang2016-03-261-1/+10
| | | | | | | | | | | | | | | | | | | | | While running tests on internal systems, we identified an issue in the startup code for newlib on AArch32 systems with Multiprocessor Extensions to the architecture. The issue is we were configuring page table flags to be Inner cacheable/Outer non-cacheable, while for at least architectures with Multiprocessor Extension, we'd configure it to Inner/Outer write-back, no write-allocate, and cacheable. The attached patch fixes this, and no regression on arm-none-eabi bare-metal tests. Adopted suggestion given by Richard offline to avoid using jump. libgloss/ * arm/cpu-init/rdimon-aem.S: Set TTBR0 to inner/outer cacheable WB, and no allocate on WB for arch with multiprocessor extension.
* or1k: properly restore timerStefan Roesch2016-03-131-1/+1
| | | | Consider the function parameter for restoring the timer
* or1k: Fix multicore stack calculationStefan Roesch2016-03-132-14/+14
| | | | | | | Change the type of the stack pointers to enable pointer calculations at byte granularity, which is needed for the calculation of _or1k_stack_core[c] and _or1k_exception_stack_core[c] with _or1k_stack_size and _or1k_exception_stack_size. (util.c:53-54)
* Remove bogus LONG(0) directives from MSP430 linker scripts.Nick Clifton2016-03-102-2/+0
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* Seperate MSP430 cio syscalls into individual function sections.Nick Clifton2016-02-091-29/+46
| | | | | | START_FUNC: New macro. END_FUNC: New macro. exit, isatty, getpid, sc2: Use the new macros.
* Make macro checks ARMv8-M baseline proofThomas Preud'homme2016-01-287-33/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | libgloss: * arm/Makefile.in: Add newlib/libc/machine/arm to the include path if newlib is present. * arm/arm.h: Include acle-compat.h. (THUMB_V7_V6M): Rename to ... (PREFER_THUMB): This. Use ACLE macros __ARM_ARCH_ISA_ARM instead of __ARM_ARCH_6M__ to decide whether to define it. (THUMB1_ONLY): Define for Thumb-1 only targets. (THUMB_V7M_V6M): Rename to ... (THUMB_VXM): This. Defined based on __ARM_ARCH_ISA_ARM, excluding ARMv7. * arm/crt0.S: Use THUMB1_ONLY rather than __ARM_ARCH_6M__, !__ARM_ARCH_ISA_ARM rather than THUMB_V7M_V6M for fp enabling, and PREFER_THUMB rather than THUMB_V7_V6M. Rename other occurences of THUMB_V7M_V6M to THUMB_VXM. * arm/linux-crt0.c: Likewise. * arm/redboot-crt0.S: Likewise. * arm/swi.h: Likewise. * arm/trap.S: Likewise. newlib: * libc/machine/arm/memcpy-stub.c: Use ACLE macros __ARM_ARCH_ISA_THUMB and __ARM_ARCH_ISA_ARM to check for Thumb-2 only targets rather than __ARM_ARCH and __ARM_ARCH_PROFILE. * libc/machine/arm/memcpy.S: Likewise. * libc/machine/arm/setjmp.S: Likewise for Thumb-1 only target and include acle-compat.h. * libc/machine/arm/strcmp.S: Likewise for Thumb-1 and Thumb-2 only target and include acle-compat.h. * libc/sys/arm/arm.h: Include acle-compat.h. (THUMB_V7_V6M): Rename to ... (PREFER_THUMB): This. Use ACLE macro __ARM_ARCH_ISA_ARM instead of __ARM_ARCH_6M__ to decide whether to define it. (THUMB1_ONLY): Define for Thumb-1 only targets. (THUMB_V7M_V6M): Rename to ... (THUMB_VXM): This. Defined based on __ARM_ARCH_ISA_ARM, excluding ARMv7. * libc/sys/arm/crt0.S: Use PREFER_THUMB rather than THUMB_V7_V6M and rename THUMB_V7M_V6M into THUMB_VXM. * libc/sys/arm/swi.h: Likewise.
* Deprecate newlib and winsup ChangeLog filesCorinna Vinschen2016-01-282-7119/+7120
| | | | Signed-off-by: Corinna Vinschen <corinna@vinschen.de>
* Build msp430-specific libnosysDJ Delorie2015-12-174-6/+12
| | | | | | | | | | The MSP430 debuggers support I/O on hardware through CIO, so we can use a CIO-enabled library as the "nosys" library (in addition to the libsim library, which talks to our simulator) * configure.in: Don't build default libnosys for msp430 * configure: Regenerate. * msp430/Makefile: Rename libcio to libnosys.
* Update CIO hooks to be more flexible.DJ Delorie2015-12-172-9/+21
| | | | | | | Replace the one hook we had with two to avoid underscore issues. * msp430/cio.c: Remove, replace with... * msp430/cio.S: New, this.
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