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| author | Andrew Haley <aph@redhat.com> | 2000-02-22 14:39:20 +0000 |
|---|---|---|
| committer | Andrew Haley <aph@redhat.com> | 2000-02-22 14:39:20 +0000 |
| commit | 95d64ccd4e4fd31d850f027fdc1030548e7a2d1e (patch) | |
| tree | a994aec3532e4a30eabd1f7c79d0d984108e7672 | |
| parent | 9d68ec8b5ce867fc4400ed8f62c4b057fe3c2508 (diff) | |
| download | cygnal-95d64ccd4e4fd31d850f027fdc1030548e7a2d1e.tar.gz cygnal-95d64ccd4e4fd31d850f027fdc1030548e7a2d1e.tar.bz2 cygnal-95d64ccd4e4fd31d850f027fdc1030548e7a2d1e.zip | |
1999-12-30 Andrew Haley <aph@cygnus.com>
* mips.h (OPCODE_IS_MEMBER): Add gp32 arg.
| -rw-r--r-- | include/opcode/ChangeLog | 4 | ||||
| -rw-r--r-- | include/opcode/mips.h | 8 |
2 files changed, 10 insertions, 2 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 2be7ead39..e8acc1c84 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,7 @@ +1999-12-30 Andrew Haley <aph@cygnus.com> + + * mips.h (OPCODE_IS_MEMBER): Add gp32 arg. + 2000-01-15 Alan Modra <alan@spri.levels.unisa.edu.au> * i386.h: Qualify intel mode far call and jmp with x_Suf. diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 8c93d1bd7..3f9207ff3 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -320,14 +320,18 @@ struct mips_opcode /* Toshiba R3900 instruction. */ #define INSN_3900 0x00000080 +/* 32-bit code running on a ISA3+ CPU. */ +#define INSN_GP32 0x00001000 + /* Test for membership in an ISA including chip specific ISAs. INSN is pointer to an element of the opcode table; ISA is the specified ISA to test against; and CPU is the CPU specific ISA to test, or zero if no CPU specific ISA test is desired. */ -#define OPCODE_IS_MEMBER(insn,isa,cpu) \ +#define OPCODE_IS_MEMBER(insn,isa,cpu,gp32) \ ((((insn)->membership & INSN_ISA) != 0 \ - && ((insn)->membership & INSN_ISA) <= isa) \ + && ((insn)->membership & INSN_ISA) <= isa \ + && ((insn)->membership & INSN_GP32 ? gp32 : 1)) \ || (cpu == 4650 \ && ((insn)->membership & INSN_4650) != 0) \ || (cpu == 4010 \ |